Computation and analysis of output error probability for C17 benchmark circuit using bayesian networks error modeling
The reliability of digital circuits is in question since the new scaled transistor technologies continue to emerge. The major factor deteriorating the circuit performance is the random and dynamic nature of errors encountered during its operation. Output-error probability is the direct measure of ci...
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| Main Authors: | , , , , |
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| Format: | Conference or Workshop Item |
| Published: |
2010
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| Subjects: | |
| Online Access: | http://eprints.utp.edu.my/4635/1/compuC17.pdf http://eprints.utp.edu.my/4635/ |
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| Summary: | The reliability of digital circuits is in question since the new scaled transistor technologies continue to emerge. The major factor deteriorating the circuit performance is the random and dynamic nature of errors encountered during its operation. Output-error probability is the direct measure of circuit's reliability. Bayesian networks error modeling is the approach used to compute error probability of digital circuits. In our paper, we have used this technique to compute and analyze the output error probability of LGSynth's C17 benchmark circuit. The simulations are based on MATLAB and show important relationships among output-error probability, execution time and number of priors involved in the analysis. |
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