Highly noise-tolerant design of digital logic gates using Markov Random Field modelling

• Main Authors: Anwer, Janhanzeb, Khalid, Usman, Hamid, Nor Hisham, Asirvadam , Vijanth Sagayan, Singh, Narenderjit
• Format: Conference or Workshop Item
• Published: 2010
• Subjects: TK Electrical engineering. Electronics Nuclear engineering; QA75 Electronic computers. Computer science; QC Physics
• Online Access: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5479997; http://eprints.utp.edu.my/3813/

Current trend of downscaling CMOS transistor dimensions is increasing the liability of digital circuits to be easily affected by noise. The resulting unexpected behaviour of our digital devices is due to the low supply voltage of these downscaled circuit elements. Though the low supply voltage decre...