Highly noise-tolerant design of digital logic gates using Markov Random Field modelling
Current trend of downscaling CMOS transistor dimensions is increasing the liability of digital circuits to be easily affected by noise. The resulting unexpected behaviour of our digital devices is due to the low supply voltage of these downscaled circuit elements. Though the low supply voltage decre...
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| Main Authors: | , , , , |
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| Format: | Conference or Workshop Item |
| Published: |
2010
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| Subjects: | |
| Online Access: | http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5479997 http://eprints.utp.edu.my/3813/ |
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