Optimization of 3-D N-channel twin silicon nanowire MOSFET
Abstract—Twin Silicon Nanowire N-channel MOSFET (n-TSNWFET) is an advanced nanotechnology which is believed to be the smallest structure of CMOS devices as well as approaching their downsized limits according to the Moore’s Law. In this work, the optimization of n-channel TSNWFET is described and ex...
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| Main Authors: | , , |
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| Format: | Conference or Workshop Item |
| Published: |
2015
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| Subjects: | |
| Online Access: | http://eprints.utm.my/id/eprint/62131/ http://mne2015.org/ |
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| Summary: | Abstract—Twin Silicon Nanowire N-channel MOSFET (n-TSNWFET) is an advanced nanotechnology which is believed to be the smallest structure of CMOS devices as well as approaching their downsized limits according to the Moore’s Law. In this work, the optimization of n-channel TSNWFET is described and explored using 3-D simulation. Electrical characteristics such as threshold voltage (Vth), subthreshold swing (SS), and ratio of Ion/Ioff are analyzed. From the results that have obtained, it is proven that better performance of the device in term of Vth, SS and leakage current (Ioff) when varying gate length (Lg), radius of nanowire channel, and gate oxide thickness (tox). |
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