A review of graphene based field effect transistor architecture and channel geometry

• Main Authors: Johari, Zaharah, Ismail, Razali
• Format: Article
• Published: American Scientific Publishers 2015
• Subjects: QC Physics
• Online Access: http://eprints.utm.my/id/eprint/55897/; http://dx.doi.org/10.1166/sam.2015.2266

The aggressive scaling of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) in nanometer scale promises low-power consumption, low energy delay product, high density as well as high processor speed. However, this phenomenon leads to short channel effects when the scaling approaches its physical limits. It becomes more challenging when the device applications are more specialized. Therefore, new device structures and the implementation of advanced materials such as graphene are necessary. Graphene is one of the materials that has been listed in International Technology Roadmap Semiconductor (ITRS) to overcome the device scaling need as the conventional silicon material reaches its ultimate limit. In this article, existing issues pertaining to graphene are reviewed. These include the electrical performance of graphene-based Field Effect Transistor (FET) using various architectures and different geometries of graphene conducting channel.