100 MS/s, 10-bit ADC using pipelined successive approximation

• Main Authors: Sarafi, Sahar, Hadidi, Kheyrollah, Abbaspour, Ebrahim, Aain, Abu Khari, Abbaszadeh, Javad
• Format: Article
• Published: World Scientific Publication 2014
• Subjects: TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://eprints.utm.my/id/eprint/51428/; http://dx.doi.org/10.1142/S0218126614500571

This paper presents an analog-to-digital converter (ADC), using pipelined successive approximation register (SAR) architecture. The structure which is a combination of SAR-ADC and pipelined ADC benefits from each of their advantages. A new synchronization method is proposed to improve the pipelined...