Configurable 2 bits per cycle successive approximation register for analog to digital converter on FPGA
Analog-to-Digital Converter (ADC) technology has been advancing to achieve a balance between speeds, size and cost. Successive approximation register (SAR) ADC is very popular for medium-to-high resolution as it is small but has difficulties in achieving high speed while flash ADC is big and not cos...
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| Main Authors: | , , , |
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| Format: | Article |
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Institute of Electrical and Electronics Engineers Inc.
2017
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| Online Access: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85011966285&doi=10.1109%2fICIAS.2016.7824120&partnerID=40&md5=3d7fc83d8e7ec9364c4374cdbdd4b73d http://eprints.utp.edu.my/20189/ |
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