100 MS/s, 10-bit ADC using pipelined successive approximation
This paper presents an analog-to-digital converter (ADC), using pipelined successive approximation register (SAR) architecture. The structure which is a combination of SAR-ADC and pipelined ADC benefits from each of their advantages. A new synchronization method is proposed to improve the pipelined...
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| Main Authors: | , , , , |
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| Format: | Article |
| Published: |
World Scientific Publication
2014
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| Subjects: | |
| Online Access: | http://eprints.utm.my/id/eprint/51428/ http://dx.doi.org/10.1142/S0218126614500571 |
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| Summary: | This paper presents an analog-to-digital converter (ADC), using pipelined successive approximation register (SAR) architecture. The structure which is a combination of SAR-ADC and pipelined ADC benefits from each of their advantages. A new synchronization method is proposed to improve the pipelined SAR-ADC's speed. The proposed method reduces the total conversion without limiting the ADC performance. To evaluate the proposed method a 10-bit 100 MS/s is designed in 0.5 μm CMOS process technology. According to the obtained simulation results, the designed ADC digitizes a 9-MHz input with 54.19 dB SNDR while consuming 57.3 mw from a 5-V supply. |
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