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100 MS/s, 10-bit ADC using pipelined successive approximation

This paper presents an analog-to-digital converter (ADC), using pipelined successive approximation register (SAR) architecture. The structure which is a combination of SAR-ADC and pipelined ADC benefits from each of their advantages. A new synchronization method is proposed to improve the pipelined...

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Main Authors: Sarafi, Sahar, Hadidi, Kheyrollah, Abbaspour, Ebrahim, Aain, Abu Khari, Abbaszadeh, Javad
Format: Article
Published: World Scientific Publication 2014
Subjects:
TK Electrical engineering. Electronics Nuclear engineering
Online Access:http://eprints.utm.my/id/eprint/51428/
http://dx.doi.org/10.1142/S0218126614500571
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spelling my.utm.514282018-03-12T03:36:32Z http://eprints.utm.my/id/eprint/51428/ 100 MS/s, 10-bit ADC using pipelined successive approximation Sarafi, Sahar Hadidi, Kheyrollah Abbaspour, Ebrahim Aain, Abu Khari Abbaszadeh, Javad TK Electrical engineering. Electronics Nuclear engineering This paper presents an analog-to-digital converter (ADC), using pipelined successive approximation register (SAR) architecture. The structure which is a combination of SAR-ADC and pipelined ADC benefits from each of their advantages. A new synchronization method is proposed to improve the pipelined SAR-ADC's speed. The proposed method reduces the total conversion without limiting the ADC performance. To evaluate the proposed method a 10-bit 100 MS/s is designed in 0.5 μm CMOS process technology. According to the obtained simulation results, the designed ADC digitizes a 9-MHz input with 54.19 dB SNDR while consuming 57.3 mw from a 5-V supply. World Scientific Publication 2014-05 Article PeerReviewed Sarafi, Sahar and Hadidi, Kheyrollah and Abbaspour, Ebrahim and Aain, Abu Khari and Abbaszadeh, Javad (2014) 100 MS/s, 10-bit ADC using pipelined successive approximation. Journal of Circuits, Systems and Computers, 23 (5). ISSN 0218-1266 http://dx.doi.org/10.1142/S0218126614500571 DOI:10.1142/S0218126614500571
institution Universiti Teknologi Malaysia
building UTM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Teknologi Malaysia
content_source UTM Institutional Repository
url_provider http://eprints.utm.my/
topic TK Electrical engineering. Electronics Nuclear engineering
spellingShingle TK Electrical engineering. Electronics Nuclear engineering
Sarafi, Sahar
Hadidi, Kheyrollah
Abbaspour, Ebrahim
Aain, Abu Khari
Abbaszadeh, Javad
100 MS/s, 10-bit ADC using pipelined successive approximation
description This paper presents an analog-to-digital converter (ADC), using pipelined successive approximation register (SAR) architecture. The structure which is a combination of SAR-ADC and pipelined ADC benefits from each of their advantages. A new synchronization method is proposed to improve the pipelined SAR-ADC's speed. The proposed method reduces the total conversion without limiting the ADC performance. To evaluate the proposed method a 10-bit 100 MS/s is designed in 0.5 μm CMOS process technology. According to the obtained simulation results, the designed ADC digitizes a 9-MHz input with 54.19 dB SNDR while consuming 57.3 mw from a 5-V supply.
format Article
author Sarafi, Sahar
Hadidi, Kheyrollah
Abbaspour, Ebrahim
Aain, Abu Khari
Abbaszadeh, Javad
author_facet Sarafi, Sahar
Hadidi, Kheyrollah
Abbaspour, Ebrahim
Aain, Abu Khari
Abbaszadeh, Javad
author_sort Sarafi, Sahar
title 100 MS/s, 10-bit ADC using pipelined successive approximation
title_short 100 MS/s, 10-bit ADC using pipelined successive approximation
title_full 100 MS/s, 10-bit ADC using pipelined successive approximation
title_fullStr 100 MS/s, 10-bit ADC using pipelined successive approximation
title_full_unstemmed 100 MS/s, 10-bit ADC using pipelined successive approximation
title_sort 100 ms/s, 10-bit adc using pipelined successive approximation
publisher World Scientific Publication
publishDate 2014
url http://eprints.utm.my/id/eprint/51428/
http://dx.doi.org/10.1142/S0218126614500571
_version_ 1643653037025132544
score 13.211869

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