Design Consideration And Impact Of Gate Length Variation On Junctionless Strained Double Gate MOSFET

• Main Authors: Kaharudin, Khairil Ezwan, Salehuddin, Fauziyah, Roslan, Ameer Farhan, Mohammed Napiah, Zul Atfyi Fauzan, Mohd Zain, Anis Suhaila
• Format: Article
• Language: English
• Published: Blue Eyes Intelligence Engineering and Sciences Publication 2019
• Online Access: http://eprints.utem.edu.my/id/eprint/24545/2/IJRTE_K.E.KAHARUDIN.PDF; http://eprints.utem.edu.my/id/eprint/24545/; https://www.ijrte.org/wp-content/uploads/papers/v8i2S6/B11460782S619.pdf

Aggressive scaling of Metal-oxide-semiconductor Field Effect Transistors (MOSFET) have been conducted over the past several decades and now is becoming more intricate due to its scaling limit and short channel effects (SCE). To overcome this adversity, a lot of new transistor structures have been proposed, including multi gate structure, high-k/metal gate stack, strained channel, fully-depleted body and junctionless configuration. This paper describes a comprehensive 2-D simulation design of a proposed transistor that employs all the aforementioned structures, named as Junctionless Strained Double Gate MOSFETs (JLSDGM). Variation in critical design parameter such as gate length (Lg) is considered and its impact on the output properties is comprehensively investigated. The results shows that the variation in gate length (Lg) does contributes a significant impact on the drain current (ID), on-current (ION), off-current (IOFF), ION/IOFF ratio, subthreshold swing (SS) and transconductance (gm). The JLSDGM device with the least investigated gate length (4nm) still provides remarkable device properties in which both ION and gm(max) are measured at 1680 µA/µm and 2.79 mS/µm respectively.