Performance Analysis Of Ultrathin Junctionless Double Gate Vertical MOSFETs
The main challenge in MOSFET minituarization is to form an ultra-shallow source/drain (S/D) junction with high doping concentration gradient, which requires an intricate S/D and channel engineering. Junctionless MOSFET configuration is an alternative solution for this issue as the junction and dopin...
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| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Institute of Advanced Engineering and Science
2019
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| Online Access: | http://eprints.utem.edu.my/id/eprint/24278/2/KEKAHARUDIN-BEEI-DEC2019.PDF http://eprints.utem.edu.my/id/eprint/24278/ https://beei.org/index.php/EEI/article/view/1615/1202 |
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| Summary: | The main challenge in MOSFET minituarization is to form an ultra-shallow source/drain (S/D) junction with high doping concentration gradient, which requires an intricate S/D and channel engineering. Junctionless MOSFET configuration is an alternative solution for this issue as the junction and doping gradients is totally eliminated. A process simulation has been developed to investigate the impact of junctionless configuration on the double-gate vertical MOSFET. The result proves that the performance of junctionless double-gate vertical MOSFETs (JLDGVM) are superior to the conventional junctioned double-gate vertical MOSFETs (JDGVM). The results reveal that the drain current (ID) of the n-JLVDGM and p-JLVDGM
could be tremendously enhanced by 57% and 60% respectively as the junctionless configuration was applied to the double-gate vertical MOSFET. In addition, junctionless devices also exhibit larger ION/IOFF ratio and smaller subthreshold slope compared to the junction devices, implying that the junctionless devices have better power consumption and faster switching capability |
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