Multiple and solid data background scheme for testing static single cell faults on SRAM memories
Memory testing is a method that requires an algorithm capable of detecting faulty memory as comprehensively as possible to facilitate the efficient manufacture of fault free memory products. Therefore, the purpose of this thesis is to introduce a Data Background (DB) scheme to generate an optimal...
Saved in:
Main Author: | Zakaria, Nor Azura |
---|---|
Format: | Thesis |
Language: | English |
Published: |
2013
|
Subjects: | |
Online Access: | http://psasir.upm.edu.my/id/eprint/84183/1/FK%202013%20142%20-%20ir.pdf http://psasir.upm.edu.my/id/eprint/84183/ |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
-
Design of CMOS potentiostat for low-concentration heavy metal detection
by: Raeisinafchi, Mehran
Published: (2015) -
Design and fabrication of a wideband CMOS continuous-time integrated baseband active filter for a synthetic aperture radar receiver
by: Faizah, Abu Bakar
Published: (2016) -
Study in Design of 32 X 4Bit Static Random Access Memory (SRAM)
by: Nor Bashariah Muhamad Bakhtiar
Published: (2008) -
Study the effect of bird’s beak on Fully Recessed LOCOS and Poly Buffered LOCOS using 2 different pad Oxide
by: Hafizal Hafiz Sarjoni
Published: (2008) -
Study of Semi-Recessed LOCOS for Quasi-nanoscale CMOS Device Isolation
by: Mohamad Idzham Abd Sani
Published: (2008)