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RF substrate noise characterization for CMOS 0.18μm

In the submicron technologies, RF noise isolation is becoming increasingly important. In this paper, the investigations of the on-chip RF isolation techniques were carried out. The chosen isolation structures were the Deep Nwell (or triple well isolation) and the P+ Guard Ring. The test structures w...

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Main Authors: Ishak, I.S., Keating, R.A., Chakrabarty, C.K.
Format: Conference Paper
Language:en_US
Published: 2017
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spelling my.uniten.dspace-57512017-12-13T08:02:19Z RF substrate noise characterization for CMOS 0.18μm Ishak, I.S. Keating, R.A. Chakrabarty, C.K. In the submicron technologies, RF noise isolation is becoming increasingly important. In this paper, the investigations of the on-chip RF isolation techniques were carried out. The chosen isolation structures were the Deep Nwell (or triple well isolation) and the P+ Guard Ring. The test structures were designed and fabricated using Silterra CMOS 0.18μm Mixed Signal process. The design parameter investigated was the distance between the isolation ring and the output terminal (Sout) in which the substrate coupling effects with and without deep nwell were characterized. © 2004 IEEE. 2017-12-08T06:45:52Z 2017-12-08T06:45:52Z 2004 Conference Paper https://www.scopus.com/record/display.uri?eid=2-s2.0-29044444843&origin=resultslist&sort=plf-f&src=s&sid=6f276876322ae7f300122ac929a2fcbe&sot en_US 2004 RF and Microwave Conference, RFM 2004 - Proceedings 2004, Pages 60-63
institution Universiti Tenaga Nasional
building UNITEN Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Tenaga Nasional
content_source UNITEN Institutional Repository
url_provider http://dspace.uniten.edu.my/
language en_US
description In the submicron technologies, RF noise isolation is becoming increasingly important. In this paper, the investigations of the on-chip RF isolation techniques were carried out. The chosen isolation structures were the Deep Nwell (or triple well isolation) and the P+ Guard Ring. The test structures were designed and fabricated using Silterra CMOS 0.18μm Mixed Signal process. The design parameter investigated was the distance between the isolation ring and the output terminal (Sout) in which the substrate coupling effects with and without deep nwell were characterized. © 2004 IEEE.
format Conference Paper
author Ishak, I.S.
Keating, R.A.
Chakrabarty, C.K.
spellingShingle Ishak, I.S.
Keating, R.A.
Chakrabarty, C.K.
RF substrate noise characterization for CMOS 0.18μm
author_facet Ishak, I.S.
Keating, R.A.
Chakrabarty, C.K.
author_sort Ishak, I.S.
title RF substrate noise characterization for CMOS 0.18μm
title_short RF substrate noise characterization for CMOS 0.18μm
title_full RF substrate noise characterization for CMOS 0.18μm
title_fullStr RF substrate noise characterization for CMOS 0.18μm
title_full_unstemmed RF substrate noise characterization for CMOS 0.18μm
title_sort rf substrate noise characterization for cmos 0.18μm
publishDate 2017
_version_ 1644493766497665024
score 13.160551

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