Effect of process parameter variability on the threshold voltage of downscaled 22nm PMOS using taguchi method

• Main Authors: Maheran, A.H.A., Menon, P.S., Shaari, S., Kalaivani, T., Ahmad, I., Faizah, Z.A.N., Apte, P.R.
• Published: 2017
• Online Access: http://dspace.uniten.edu.my:8080/jspui/handle/123456789/5211

This paper provides the enhancement of 22nm planar PMOS transistor technology through downscaling, design parameter simulation and optimization process. The scaled down device is optimized for its process parameter variability using Taguchi method. The aim is to find the best combination of fabricat...