VHDL simulation of reset automatic block, 64 bit latch block, and test complete blocks for PD detection circuit system using FPGA

• Main Authors: Emilliano, Chakrabarty C.K., Ghani A.B.A., Ramasamy A.K.
• Other Authors: 35974769600
• Format: Conference paper
• Published: 2023
• Subjects: ADC with peak detector block; Counter with reset block; FPGA simulation; FPGA technology; Partial discharge detection; Real time processing; Underground cable; VHDL programming; Cables; Computer hardware description languages; Field programmable gate arrays (FPGA); Partial discharges; Research; Signal detection; Technology; Underground cables; Peak detectors; Realtime processing; Detectors

This paper is purely a model to determine the design circuit to implement Partial Discharge (PD) detection in FPGA technology. The research shall involve ISE Simulator version 10.1i (Xilinx) and ISE Xilinx Synthesized Technology (XST) using Very high integrated circuit Hardware Description Language...