VHDL simulation of reset automatic block, 64 bit latch block, and test complete blocks for PD detection circuit system using FPGA

• Main Authors: Emilliano, Chakrabarty C.K., Ghani A.B.A., Ramasamy A.K.
• Other Authors: 35974769600
• Format: Conference paper
• Published: 2023
• Subjects: ADC with peak detector block; Counter with reset block; FPGA simulation; FPGA technology; Partial discharge detection; Real time processing; Underground cable; VHDL programming; Cables; Computer hardware description languages; Field programmable gate arrays (FPGA); Partial discharges; Research; Signal detection; Technology; Underground cables; Peak detectors; Realtime processing; Detectors

This paper is purely a model to determine the design circuit to implement Partial Discharge (PD) detection in FPGA technology. The research shall involve ISE Simulator version 10.1i (Xilinx) and ISE Xilinx Synthesized Technology (XST) using Very high integrated circuit Hardware Description Language (VHDL) programming to evaluate the use of Field Programming Gate Array (FPGA) for the detection and counting of partial discharge signals in high voltage underground cable. The impulse signals at the input data have very fast rise time in the range of 1 ns to 2 ns. The output signals of peak detector block, 64 bit BCD counter with reset block and reset automatic block is processed using reset automatic block and 64 bit latch block for keep output data in LCD to constant when the 64 bit BCD counter block is reset and return to zero again until update new data again. The combination of all blocks of PD detection circuit system is tested by using ISE simulator. In the next stage, this method will be implemented on a lab simulation scale for testing and validation. � 2010 IEEE.