Staff View: VHDL simulation of reset automatic block, 64 bit latch block, and test complete blocks for PD detection circuit system using FPGA

VHDL simulation of reset automatic block, 64 bit latch block, and test complete blocks for PD detection circuit system using FPGA

This paper is purely a model to determine the design circuit to implement Partial Discharge (PD) detection in FPGA technology. The research shall involve ISE Simulator version 10.1i (Xilinx) and ISE Xilinx Synthesized Technology (XST) using Very high integrated circuit Hardware Description Language...

Full description

Saved in:

Bibliographic Details
Main Authors:	Emilliano, Chakrabarty C.K., Ghani A.B.A., Ramasamy A.K.
Other Authors:	35974769600
Format:	Conference paper
Published:	2023
Subjects:	ADC with peak detector block Counter with reset block FPGA simulation FPGA technology Partial discharge detection Real time processing Underground cable VHDL programming Cables Computer hardware description languages Field programmable gate arrays (FPGA) Partial discharges Research Signal detection Technology Underground cables Peak detectors Realtime processing Detectors
Tags:	Add Tag No Tags, Be the first to tag this record!

id	my.uniten.dspace-30546
record_format	dspace
spelling	my.uniten.dspace-305462023-12-29T15:49:15Z VHDL simulation of reset automatic block, 64 bit latch block, and test complete blocks for PD detection circuit system using FPGA Emilliano Chakrabarty C.K. Ghani A.B.A. Ramasamy A.K. 35974769600 6701755282 24469638000 16023154400 ADC with peak detector block Counter with reset block FPGA simulation FPGA technology Partial discharge detection Real time processing Underground cable VHDL programming Cables Computer hardware description languages Field programmable gate arrays (FPGA) Partial discharges Research Signal detection Technology Underground cables Counter with reset block FPGA simulation FPGA technology Partial discharge detection Peak detectors Realtime processing VHDL programming Detectors This paper is purely a model to determine the design circuit to implement Partial Discharge (PD) detection in FPGA technology. The research shall involve ISE Simulator version 10.1i (Xilinx) and ISE Xilinx Synthesized Technology (XST) using Very high integrated circuit Hardware Description Language (VHDL) programming to evaluate the use of Field Programming Gate Array (FPGA) for the detection and counting of partial discharge signals in high voltage underground cable. The impulse signals at the input data have very fast rise time in the range of 1 ns to 2 ns. The output signals of peak detector block, 64 bit BCD counter with reset block and reset automatic block is processed using reset automatic block and 64 bit latch block for keep output data in LCD to constant when the 64 bit BCD counter block is reset and return to zero again until update new data again. The combination of all blocks of PD detection circuit system is tested by using ISE simulator. In the next stage, this method will be implemented on a lab simulation scale for testing and validation. � 2010 IEEE. Final 2023-12-29T07:49:15Z 2023-12-29T07:49:15Z 2010 Conference paper 10.1109/ICSGRC.2010.5562530 2-s2.0-77957995643 https://www.scopus.com/inward/record.uri?eid=2-s2.0-77957995643&doi=10.1109%2fICSGRC.2010.5562530&partnerID=40&md5=c6be657a6c4b937aae2e6ca46681aa43 https://irepository.uniten.edu.my/handle/123456789/30546 5562530 14 19 Scopus
institution	Universiti Tenaga Nasional
building	UNITEN Library
collection	Institutional Repository
continent	Asia
country	Malaysia
content_provider	Universiti Tenaga Nasional
content_source	UNITEN Institutional Repository
url_provider	http://dspace.uniten.edu.my/
topic	ADC with peak detector block Counter with reset block FPGA simulation FPGA technology Partial discharge detection Real time processing Underground cable VHDL programming Cables Computer hardware description languages Field programmable gate arrays (FPGA) Partial discharges Research Signal detection Technology Underground cables Counter with reset block FPGA simulation FPGA technology Partial discharge detection Peak detectors Realtime processing VHDL programming Detectors
spellingShingle	ADC with peak detector block Counter with reset block FPGA simulation FPGA technology Partial discharge detection Real time processing Underground cable VHDL programming Cables Computer hardware description languages Field programmable gate arrays (FPGA) Partial discharges Research Signal detection Technology Underground cables Counter with reset block FPGA simulation FPGA technology Partial discharge detection Peak detectors Realtime processing VHDL programming Detectors Emilliano Chakrabarty C.K. Ghani A.B.A. Ramasamy A.K. VHDL simulation of reset automatic block, 64 bit latch block, and test complete blocks for PD detection circuit system using FPGA
description	This paper is purely a model to determine the design circuit to implement Partial Discharge (PD) detection in FPGA technology. The research shall involve ISE Simulator version 10.1i (Xilinx) and ISE Xilinx Synthesized Technology (XST) using Very high integrated circuit Hardware Description Language (VHDL) programming to evaluate the use of Field Programming Gate Array (FPGA) for the detection and counting of partial discharge signals in high voltage underground cable. The impulse signals at the input data have very fast rise time in the range of 1 ns to 2 ns. The output signals of peak detector block, 64 bit BCD counter with reset block and reset automatic block is processed using reset automatic block and 64 bit latch block for keep output data in LCD to constant when the 64 bit BCD counter block is reset and return to zero again until update new data again. The combination of all blocks of PD detection circuit system is tested by using ISE simulator. In the next stage, this method will be implemented on a lab simulation scale for testing and validation. � 2010 IEEE.
author2	35974769600
author_facet	35974769600 Emilliano Chakrabarty C.K. Ghani A.B.A. Ramasamy A.K.
format	Conference paper
author	Emilliano Chakrabarty C.K. Ghani A.B.A. Ramasamy A.K.
author_sort	Emilliano
title	VHDL simulation of reset automatic block, 64 bit latch block, and test complete blocks for PD detection circuit system using FPGA
title_short	VHDL simulation of reset automatic block, 64 bit latch block, and test complete blocks for PD detection circuit system using FPGA
title_full	VHDL simulation of reset automatic block, 64 bit latch block, and test complete blocks for PD detection circuit system using FPGA
title_fullStr	VHDL simulation of reset automatic block, 64 bit latch block, and test complete blocks for PD detection circuit system using FPGA
title_full_unstemmed	VHDL simulation of reset automatic block, 64 bit latch block, and test complete blocks for PD detection circuit system using FPGA
title_sort	vhdl simulation of reset automatic block, 64 bit latch block, and test complete blocks for pd detection circuit system using fpga
publishDate	2023
_version_	1806424004779573248
score	13.214268

VHDL simulation of reset automatic block, 64 bit latch block, and test complete blocks for PD detection circuit system using FPGA

Similar Items