Analyze and optimize the silicide thickness in 45nm CMOS technology using Taguchi method

• Main Authors: Salehuddin F., Ahmad I., Hamid F.A., Zaharim A.
• Other Authors: 36239165300
• Format: Conference Paper
• Published: 2023
• Subjects: Cobalt salicide; Optimizations of 45nm CMOS; Silvaco; Taguchi method; CMOS integrated circuits; Cobalt; Cobalt compounds; Design; Optimization; Semiconductor growth; Silicides; Taguchi methods; Threshold voltage; Anneal temperatures; CMOS technology; Design time; Design tool; Electrical characterization; Experimental data; Halo implantation; NMOS devices; Optimal process; Optimizers; Oxide growth; PMOS devices; Process parameters; Response characteristic; Taguchi; MOS devices

Taguchi method was used to analyze the experimental data in order to get the optimum average of silicide thickness in 45nm devices. The virtually fabrication of the devices was performed by using ATHENA module. While the electrical characterization of the devices was implemented by using ATLAS module. These two modules were used as design tools and helps to reduce design time and cost. In this paper, both modules and Taguchi method was combined to aid in design and optimizer the process parameters. There are four process parameters (factors), namely Halo Implantation, Source/Drain (S/D) Implantation, Oxide Growth Temperature and Silicide Anneal temperature. These factors were varied for 3 levels to perform 9 experiments. Threshold voltage (VTH) results were used as the evaluation variables. Then, the results were subjected to the Taguchi method for determine the optimal process parameters and to produce predicted values. The predicted values of the process parameters were successfully verified with ATHENA and ATLAS's simulator. The results show that the average of silicide thickness after optimizations approaches was 30.66nm and 30.58nm for NMOS and PMOS devices respectively. In this research, Halo Implantation was identified as one of the process parameters that has the strongest effect on the response characteristics. While the S/D Implantation was identified as an adjustment factor to get the nominal values of threshold voltage for PMOS and NMOS devices equal to -0.1501V and +0.150047V respectively. � 2010 IEEE.