Characterization and optimizations of silicide thickness in 45nm pMOS device
The characteristics of high performance 45nm pMOS devices based on International Technology Roadmap for Semiconductor (ITRS) have been studied using ATHENA and ATLAS's simulator. There are four factors were varied for 3 levels to perform 9 experiments. The factors are halo implantation, Source/...
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my.uniten.dspace-296492024-04-18T10:25:40Z Characterization and optimizations of silicide thickness in 45nm pMOS device Salehuddin F. Ahmad I. Hamid F.A. Zaharim A. 36239165300 12792216600 6603573875 15119466900 45nm pMOS Cobalt salicide Optimization Taguchi method Cobalt Cobalt compounds Optimization Polysilicon Semiconductor devices Semiconductor growth Silicides Taguchi methods Thermoelectric equipment 45nm pMOS Anneal temperatures Cobalt salicide Experimental data Gate electrode resistance Halo implantation International Technology Roadmap for Semiconductors Optimum solution Oxide growth PMOS devices Poly-si gates Electron devices The characteristics of high performance 45nm pMOS devices based on International Technology Roadmap for Semiconductor (ITRS) have been studied using ATHENA and ATLAS's simulator. There are four factors were varied for 3 levels to perform 9 experiments. The factors are halo implantation, Source/Drain (S/D) implantation, oxide growth temperature and silicide anneal temperature. In this paper, Taguchi Method was used to analyze the experimental data in order to get the optimum solutions for these factors. The silicide on the poly-Si gate electrode has been used to reduce the gate electrode resistance. The result shows that the threshold voltage (VTH) value is -0.1501 Volts. The value is exactly same with ITRS prediction. This shows that Taguchi Method is a very useful tool to predict the optimum solution in finding the 45nm pMOS fabrication recipes with appropriate VTH value. The result also shows that the average of silicide thickness after optimizations approaches is 30.12nm. �2010 IEEE. Final 2023-12-28T07:17:53Z 2023-12-28T07:17:53Z 2010 Conference Paper 10.1109/ICEDSA.2010.5503054 2-s2.0-77955297325 https://www.scopus.com/inward/record.uri?eid=2-s2.0-77955297325&doi=10.1109%2fICEDSA.2010.5503054&partnerID=40&md5=44e1abb946199d0e2cfd7a60b4738e59 https://irepository.uniten.edu.my/handle/123456789/29649 5503054 300 304 Scopus |
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45nm pMOS Cobalt salicide Optimization Taguchi method Cobalt Cobalt compounds Optimization Polysilicon Semiconductor devices Semiconductor growth Silicides Taguchi methods Thermoelectric equipment 45nm pMOS Anneal temperatures Cobalt salicide Experimental data Gate electrode resistance Halo implantation International Technology Roadmap for Semiconductors Optimum solution Oxide growth PMOS devices Poly-si gates Electron devices |
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45nm pMOS Cobalt salicide Optimization Taguchi method Cobalt Cobalt compounds Optimization Polysilicon Semiconductor devices Semiconductor growth Silicides Taguchi methods Thermoelectric equipment 45nm pMOS Anneal temperatures Cobalt salicide Experimental data Gate electrode resistance Halo implantation International Technology Roadmap for Semiconductors Optimum solution Oxide growth PMOS devices Poly-si gates Electron devices Salehuddin F. Ahmad I. Hamid F.A. Zaharim A. Characterization and optimizations of silicide thickness in 45nm pMOS device |
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The characteristics of high performance 45nm pMOS devices based on International Technology Roadmap for Semiconductor (ITRS) have been studied using ATHENA and ATLAS's simulator. There are four factors were varied for 3 levels to perform 9 experiments. The factors are halo implantation, Source/Drain (S/D) implantation, oxide growth temperature and silicide anneal temperature. In this paper, Taguchi Method was used to analyze the experimental data in order to get the optimum solutions for these factors. The silicide on the poly-Si gate electrode has been used to reduce the gate electrode resistance. The result shows that the threshold voltage (VTH) value is -0.1501 Volts. The value is exactly same with ITRS prediction. This shows that Taguchi Method is a very useful tool to predict the optimum solution in finding the 45nm pMOS fabrication recipes with appropriate VTH value. The result also shows that the average of silicide thickness after optimizations approaches is 30.12nm. �2010 IEEE. |
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36239165300 |
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36239165300 Salehuddin F. Ahmad I. Hamid F.A. Zaharim A. |
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Conference Paper |
author |
Salehuddin F. Ahmad I. Hamid F.A. Zaharim A. |
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Salehuddin F. |
title |
Characterization and optimizations of silicide thickness in 45nm pMOS device |
title_short |
Characterization and optimizations of silicide thickness in 45nm pMOS device |
title_full |
Characterization and optimizations of silicide thickness in 45nm pMOS device |
title_fullStr |
Characterization and optimizations of silicide thickness in 45nm pMOS device |
title_full_unstemmed |
Characterization and optimizations of silicide thickness in 45nm pMOS device |
title_sort |
characterization and optimizations of silicide thickness in 45nm pmos device |
publishDate |
2023 |
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1806425497942360064 |
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13.19449 |