Application of Taguchi method in the optimization of process variation for 32nm CMOS technology

• Main Authors: Elgomati H.A., Majlis B.Y., Ahmad I., Salehuddin F., Hamid F.A., Zaharim A., Apte P.R.
• Other Authors: 36536722700
• Format: Article
• Published: 2023
• Subjects: Compensation implantation; HALO; S/D implantation; Silicon MOSFET 32nm; Taguchi method; Threshold voltage

In this paper, we investigate the effect of four process parameters namely HALO implantation, compensation implantations, SiO2 thickness and silicide annealing time on threshold voltage (VTH) in complementary metal oxide semiconductor (CMOS) technology. The setting of process parameters were determi...