Optimization of process parameter variation in 45nm p-channel MOSFET using L18 orthogonal array

• Main Authors: Salehuddin F., Ahmad I., Hamid F.A., Zaharim A., Hamid A.M.A., Menon P.S., Elgomati H.A., Majlis B.Y., Apte P.R.
• Other Authors: 36239165300
• Format: Conference paper
• Published: 2023
• Subjects: Leakage Current; NMOS Device; Taguchi Method; Threshold Voltage; Electron beam lithography; Experiments; Leakage currents; Optimization; Simulators; Taguchi methods; Threshold voltage; 3 levels; Adjustment factors; Control factors; Device simulators; Major factors; MOS-FET; NMOS devices; Noise factor; Nominal values; Optimization of process parameters; Orthogonal array; P channels; Performance characteristics; pMOS devices; Process parameters; Process simulators; Signal to noise (S/N) ratios; MOSFET devices

In this study, orthogonal array of L18 in Taguchi method was used to optimize the process parameters variance on threshold voltage (V TH) in 45nm p-channel Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device. The signal-to-noise (S/N) ratio and analysis of variance (ANOVA) are employed to study the performance characteristics of the PMOS device. There are eight process parameters (control factors) were varied for 2 and 3 levels to performed 18 experiments. Whereas, the two noise factors were varied for 2 levels to get four readings of VTH for every row of experiment. VTH results were used as the evaluation variable. This work was done using TCAD simulator, consisting of a process simulator, ATHENA and device simulator, ATLAS. These two simulators were combined with L 18 Orthogonal Array to aid in design and optimize the process parameters. The predicted values of the process parameters were verified successfully with ATHENA and ATLAS's simulator. In PMOS device, VTH implant dose (26%) and compensate implant dose (26%) were the major factors affecting the threshold voltage. While S/D Implant was identified as an adjustment factor in PMOS device. These adjustment factors have been used to get the nominal values of threshold voltage for PMOS device closer to -0.289V. � 2012 IEEE.