Modeling and optimizing of threshold voltage of 32nm NMOS transistor using L18 orthogonal array Taguchi method

• 主要な著者: Elgomati H.A., Majlis B.Y., Ahmad I.
• その他の著者: 36536722700
• フォーマット: Conference paper
• 出版事項: 2023
• 主題: Compensation Implantation; HALO; S/D implantation; Silicon MOSFET 32nm; Taguchi L18; Taguchi Method; Threshold voltage

This paper describes our investigation of the effect of seven processes' parameters on threshold voltage (VTH) in the fabrication of a 32nm CMOS transistor. The parameters are HALO implantation, S/D Implantation, Compensation implantations, SiO2 thickness, VTH adjustment implantation, polysilic...