FSM based green memory design and its implementation on ultrascale plus FPGA
In this work, we are going to design a memory using Verilog programming in Vivado 2018.3 Integrated Development Environment and implement it on Kintex UltraScale+ FPGA. In order to make it green, we are reducing power dissipation of our design using power supply settings of UltraScale FPGA that supp...
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Main Authors: | Pandey B., Mohamed R.R., Tomar G.S., Hussain D.M.A., Baker El-Biary Y.A. |
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Other Authors: | 57203239026 |
Format: | Article |
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Innovare Academics Sciences Pvt. Ltd
2023
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