Hardware transactional memory architecture with adaptive version management for multi-processor FPGA platforms

• Main Authors: Sirkunan, J., Ooi, C. Y., Shaikh-Husin, N., Hau, Y. W., Marsono, M. N.
• Format: Article
• Published: Elsevier B.V. 2017
• Subjects: TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://eprints.utm.my/id/eprint/76556/; https://www.scopus.com/inward/record.uri?eid=2-s2.0-85009461089&doi=10.1016%2fj.sysarc.2016.12.006&partnerID=40&md5=c3137ad393030934ea9c17083a64cc28

Multiprocessor embedded systems integrates diverse dedicated processing units to handle high performance applications such as in multimedia and network processing. However, lock-based synchronization limits the efficiency of such heterogeneous concurrent systems. Hardware Transactional Memory (HTM)...