Probability Formulation of Soft Error in Memory Circuit

• Main Authors: Norhuzaimin, Julai, Farhana, Mohamad, Rohana, Sapawi, Shamsiah, Suhaili
• Format: Article
• Language: English
• Published: UPM Press 2023
• Subjects: TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://ir.unimas.my/id/eprint/44815/1/Probability%20Formulation%20of%20Soft%20Error.pdf; http://ir.unimas.my/id/eprint/44815/; http://www.pertanika.upm.edu.my/pjst/browse/regular-issue?article=JST-3732-2022; https://doi.org/10.47836/pjst.31.4.19

Downscaling threatens the designers invested in integrity and error mitigation against soft errors. This study formulated the probability of soft error changing the logic state of a Differential Logic with an Inverter Latch (DIL). Using Cadence Virtuoso, current pulses were injected into various nodes in stages until a logic flip was instigated. The voltage and temperature parameters were increased to observe the current level changes over time. The critical charge from each stage was obtained, and a method to formulate the probability of each instance was developed. The voltage produced a higher effect of the change to the critical charge of any instance as compared to temperature. The findings revealed that the N-channel metal-oxide semiconductor (NMOS) drain is more vulnerable to temperature and voltage variation than P-channel metal-oxide semiconductor (PMOS).