Optimization of Resistance Load in 4T-Static Random-Access Memory Cell Based on Silicon Nanowire Transistor

• Main Author: Hashim, Yasir
• Format: Article
• Language: English; English
• Published: American Scientific Publishers 2018
• Subjects: TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://umpir.ump.edu.my/id/eprint/19249/1/17JNN-13956.pdf; http://umpir.ump.edu.my/id/eprint/19249/7/ftech-2018-yasir.pdf; http://umpir.ump.edu.my/id/eprint/19249/; https://doi.org/10.1166/jnn.2018.13956; https://doi.org/10.1166/jnn.2018.13956

This study explores optimization of resistance load (R-Load) of four silicon nanowire transistor (SiNWT)-based static random-access memory (SRAM) cell. Noise margins and inflection voltage of butterfly characteristics with static power consumption of SRAM cell are used as limiting factors in this optimization. Range of R-Load used in this study was 20–1000 KΩ with V dd= 1 V. Results indicate that optimization depends critically on resistance load value. The optimized range of R-Load is 100–200 KΩ.