Optimization of Resistance Load in 4T-Static Random-Access Memory Cell Based on Silicon Nanowire Transistor
This study explores optimization of resistance load (R-Load) of four silicon nanowire transistor (SiNWT)-based static random-access memory (SRAM) cell. Noise margins and inflection voltage of butterfly characteristics with static power consumption of SRAM cell are used as limiting factors in this op...
Saved in:
| Main Author: | |
|---|---|
| Format: | Article |
| Language: | English English |
| Published: |
American Scientific Publishers
2018
|
| Subjects: | |
| Online Access: | http://umpir.ump.edu.my/id/eprint/19249/1/17JNN-13956.pdf http://umpir.ump.edu.my/id/eprint/19249/7/ftech-2018-yasir.pdf http://umpir.ump.edu.my/id/eprint/19249/ https://doi.org/10.1166/jnn.2018.13956 https://doi.org/10.1166/jnn.2018.13956 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| Summary: | This study explores optimization of resistance load (R-Load) of four silicon nanowire transistor (SiNWT)-based static random-access memory (SRAM) cell. Noise margins and inflection voltage of butterfly characteristics with static power consumption of SRAM cell are used as limiting factors in this optimization. Range of R-Load used in this study was 20–1000 KΩ with V dd= 1 V. Results indicate that optimization depends critically on resistance load value. The optimized range of R-Load is 100–200 KΩ. |
|---|