Design Common Mode Logic(CML) Frequency Divider in CMOS Porcess Technology
The objective of this project is to design current mode logic (CML) frequency divider in CMOS technology. The current spikes that occur during transition between tacking and latch mode in transistor will degrade the performance of the frequency divider. The parasitic capacitances that exist in tw...
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| Format: | Final Year Project |
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Universiti Teknologi Petronas
2009
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| Online Access: | http://utpedia.utp.edu.my/1048/ |
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