Study on Delay Design-for-Testability for Functional RTL Circuits
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oai:utpedia.utp.edu.my:255312023-10-03T03:53:36Z http://utpedia.utp.edu.my/id/eprint/25531/ Study on Delay Design-for-Testability for Functional RTL Circuits Shaheen, Ateeq Ur Rehman TK Electrical engineering. Electronics Nuclear engineering 2017 Thesis NonPeerReviewed Shaheen, Ateeq Ur Rehman (2017) Study on Delay Design-for-Testability for Functional RTL Circuits. Doctoral thesis, Universiti Teknologi PETRONAS. |
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TK Electrical engineering. Electronics Nuclear engineering |
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TK Electrical engineering. Electronics Nuclear engineering Shaheen, Ateeq Ur Rehman Study on Delay Design-for-Testability for Functional RTL Circuits |
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Thesis |
author |
Shaheen, Ateeq Ur Rehman |
author_facet |
Shaheen, Ateeq Ur Rehman |
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Shaheen, Ateeq Ur Rehman |
title |
Study on Delay Design-for-Testability for Functional RTL Circuits |
title_short |
Study on Delay Design-for-Testability for Functional RTL Circuits |
title_full |
Study on Delay Design-for-Testability for Functional RTL Circuits |
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Study on Delay Design-for-Testability for Functional RTL Circuits |
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Study on Delay Design-for-Testability for Functional RTL Circuits |
title_sort |
study on delay design-for-testability for functional rtl circuits |
publishDate |
2017 |
url |
http://utpedia.utp.edu.my/id/eprint/25531/ |
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1779440868685512704 |
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13.154905 |