Study on Delay Design-for-Testability for Functional RTL Circuits

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Main Author: Shaheen, Ateeq Ur Rehman
Format: Thesis
Published: 2017
Subjects:
Online Access:http://utpedia.utp.edu.my/id/eprint/25531/
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id oai:utpedia.utp.edu.my:25531
record_format eprints
spelling oai:utpedia.utp.edu.my:255312023-10-03T03:53:36Z http://utpedia.utp.edu.my/id/eprint/25531/ Study on Delay Design-for-Testability for Functional RTL Circuits Shaheen, Ateeq Ur Rehman TK Electrical engineering. Electronics Nuclear engineering 2017 Thesis NonPeerReviewed Shaheen, Ateeq Ur Rehman (2017) Study on Delay Design-for-Testability for Functional RTL Circuits. Doctoral thesis, Universiti Teknologi PETRONAS.
institution Universiti Teknologi Petronas
building UTP Resource Centre
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Teknologi Petronas
content_source UTP Electronic and Digitized Intellectual Asset
url_provider http://utpedia.utp.edu.my/
topic TK Electrical engineering. Electronics Nuclear engineering
spellingShingle TK Electrical engineering. Electronics Nuclear engineering
Shaheen, Ateeq Ur Rehman
Study on Delay Design-for-Testability for Functional RTL Circuits
format Thesis
author Shaheen, Ateeq Ur Rehman
author_facet Shaheen, Ateeq Ur Rehman
author_sort Shaheen, Ateeq Ur Rehman
title Study on Delay Design-for-Testability for Functional RTL Circuits
title_short Study on Delay Design-for-Testability for Functional RTL Circuits
title_full Study on Delay Design-for-Testability for Functional RTL Circuits
title_fullStr Study on Delay Design-for-Testability for Functional RTL Circuits
title_full_unstemmed Study on Delay Design-for-Testability for Functional RTL Circuits
title_sort study on delay design-for-testability for functional rtl circuits
publishDate 2017
url http://utpedia.utp.edu.my/id/eprint/25531/
_version_ 1779440868685512704
score 13.154905