Delay Design-for-Testability for Functional RTL Circuits

• Main Authors: Shaheen, Ateeq-Ur-Rehman, Hussin, Fawnizu Azmadi, Hamid, Nor Hisham
• Format: Conference or Workshop Item
• Published: 2015
• Online Access: http://eprints.utp.edu.my/11959/1/ICITEE2015.pdf; http://eprints.utp.edu.my/11959/

Design-for-testability (DFT) reduces the test complexity of sequential register-transfer-level (RTL) circuits. Only enhanced scan technique from the scan based approaches guarantee two pattern testability with a large area and test time overhead. This paper proposes a path delay DFT tec...