Design of an All-Digital Synchronized Frequency Multiplier Based on a Dual-Loop (D/FLL) Architecture
This paper presents a new architecture for a synchronized frequency multiplier circuit. The proposed architecture is an all-digital dual-loop delay- and frequency-locked loops circuit, which has several advantages, namely, it does not have the jitter accumulation issue that is normally encountered i...
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| Main Authors: | , |
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| Format: | Citation Index Journal |
| Published: |
2012
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| Subjects: | |
| Online Access: | http://eprints.utp.edu.my/9003/2/546212.pdf http://eprints.utp.edu.my/9003/ |
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