Pipelined architecture for low density parity check encoder
This paper proposes a pipelined architecture for low density parity check encoder by pipelining information bits and sub-matrices of parity check matrix (H) using two bit-wise operations. The two bit-wise operations are multiplication and exclusive-OR. The investigation is done by exploring two meth...
Saved in:
| Main Authors: | , , |
|---|---|
| Format: | Conference or Workshop Item |
| Published: |
2012
|
| Subjects: | |
| Online Access: | http://eprints.utp.edu.my/8826/1/06306129.pdf http://dx.doi.org/10.1109/ICIAS.2012.6306129 http://eprints.utp.edu.my/8826/ |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| Summary: | This paper proposes a pipelined architecture for low density parity check encoder by pipelining information bits and sub-matrices of parity check matrix (H) using two bit-wise operations. The two bit-wise operations are multiplication and exclusive-OR. The investigation is done by exploring two methods of pipelining using the two bit-wise operations in the proposed architecture. The first method of pipelining uses combination of shift register and memory for the sub-matrices of H while the second method of pipelining uses shift register for the information bits and the sub-matrices of H. It is shown that the second method of pipelining increases the throughput but has the largest units of shift registers and flip-flops in the design. |
|---|