High Throughput Architecture for Low Density Parity Check (LDPC) Encoder

This paper proposes a bit-wise matrix-vector multiplication in the optimization of a proposed low density parity check (LDPC) encoder. Investigation of this proposed architecture is done by implementing five code lengths using one IEEE 802.16e standard code rate. It is shown that the proposed archit...

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Bibliographic Details
Main Authors: Anggraeni, Silvia, Hussin, Fawnizu Azmadi, Jeoti , Varun
Format: Conference or Workshop Item
Published: 2013
Online Access:http://eprints.utp.edu.my/11981/1/ArchEncLDPC.pdf
http://eprints.utp.edu.my/11981/
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