Fault Modeling of Analog Circuits Using System Identification Automated Model Generation Approaches from SPICE level Descriptions
Fault modeling and simulation (FMAS) of analog circuits is considered to be time consuming and expensive as compared to digital circuits. FMAS of analog circuits is heavily dependent on transistor level (TL) circuits and slow speed of TL fault simulation (TLFS) increase overall testing cost. Therefo...
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| Main Authors: | , , , |
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| Format: | Article |
| Published: |
American Scientific Publishers
2012
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| Subjects: | |
| Online Access: | http://eprints.utp.edu.my/8437/1/ICAEE2012_210.pdf http://www.aspbs.com/science.htm http://eprints.utp.edu.my/8437/ |
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