Delay Fault Modelling/Simulation using VHDL-AMS in Multi Vdd Systems

With the growing density of Very Large Scale Integrated(VLSI circuits, traditional digital fault simulation is no longer a viable option. This is because of analogue-like behaviour in digital circuits. The need for fast fault simulation is one of the main requirements in test pattern generation. The...

Full description

Saved in:
Bibliographic Details
Main Authors: Zain Ali, Noohul Basheer, Mark, Zwolinski, Ahmadi, Arash
Format: Conference or Workshop Item
Published: 2008
Subjects:
Online Access:http://eprints.utp.edu.my/4806/1/Delay_Fault_ModellingSimulationusingVHDL-AMSinMulti-VddSystems.pdf
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4559309
http://eprints.utp.edu.my/4806/
Tags: Add Tag
No Tags, Be the first to tag this record!