Hardware Implementation of an Optimized Processor Architecture for SOBEL Image Edge Detection Operator
This paper presents an implementation of a dedicated processor for image edge detection on field programmable gate arrays (FPGAs). The processor architecture is originally a Sobel based edge detection filter optimized to minimize memory utilization, redundant calculations and hence, overall logic re...
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my.utp.eprints.42352017-01-19T08:24:01Z Hardware Implementation of an Optimized Processor Architecture for SOBEL Image Edge Detection Operator M. Osman, Zahraa Elhassan Hussin, Fawnizu Azmadi Zain Ali, Noohul Basheer TK Electrical engineering. Electronics Nuclear engineering This paper presents an implementation of a dedicated processor for image edge detection on field programmable gate arrays (FPGAs). The processor architecture is originally a Sobel based edge detection filter optimized to minimize memory utilization, redundant calculations and hence, overall logic resources used to implement the processor on FPGA. The optimization is achieved by exploiting the FPGAs' high parallelism, flexibility and I/O bandwidth. Results show that our optimized processor architecture uses 22% less Adaptive Lookup Tables (ALUTs) 40% less dedicated logic registers and 10% overall logic resources utilization reduction over basic architecture in [1] when implemented on Stratix II EP2S60. The optimization makes the processor feasible to be used for applications like embedded video processing. 2010-06-15 Conference or Workshop Item NonPeerReviewed application/pdf http://eprints.utp.edu.my/4235/1/icias-zahraa.pdf%3Fattachauth%3DANoY7crGR_WIYeVabAL__dLRXvdX42BGyBR4YsQ9Kkx6IwE8CDbXtNR7_0B_ZTgvdQGBS4SOvZFnup4DYCRrKwVdBQDpkxCwTpPqxN0UBWC3qDBZtA0dFY_NPY_dOzLFSa8s1EK1SNOH2pIE_su-IOue63oC2sz7OYRD1gJpUHOQDPUlyNxbDAH186cC76O_g8YrPrRtGEjq%26attredirects%3D0 http://www.utp.edu.my/icias2010/ M. Osman, Zahraa Elhassan and Hussin, Fawnizu Azmadi and Zain Ali, Noohul Basheer (2010) Hardware Implementation of an Optimized Processor Architecture for SOBEL Image Edge Detection Operator. In: International Conference on Intelligent and Advanced Systems (ICIAS 2010), 15-17 June, 2010, Kuala Lumpur, Malaysia. http://eprints.utp.edu.my/4235/ |
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TK Electrical engineering. Electronics Nuclear engineering M. Osman, Zahraa Elhassan Hussin, Fawnizu Azmadi Zain Ali, Noohul Basheer Hardware Implementation of an Optimized Processor Architecture for SOBEL Image Edge Detection Operator |
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This paper presents an implementation of a dedicated processor for image edge detection on field programmable gate arrays (FPGAs). The processor architecture is originally a Sobel based edge detection filter optimized to minimize memory utilization, redundant calculations and hence, overall logic resources used to implement the processor on FPGA. The optimization is achieved by exploiting the FPGAs' high parallelism, flexibility and I/O bandwidth. Results show that our optimized processor architecture uses 22% less Adaptive Lookup Tables (ALUTs) 40% less dedicated logic registers and 10% overall logic resources utilization reduction over basic architecture in [1] when implemented on Stratix II EP2S60. The optimization makes the processor feasible to be used for applications like embedded video processing. |
format |
Conference or Workshop Item |
author |
M. Osman, Zahraa Elhassan Hussin, Fawnizu Azmadi Zain Ali, Noohul Basheer |
author_facet |
M. Osman, Zahraa Elhassan Hussin, Fawnizu Azmadi Zain Ali, Noohul Basheer |
author_sort |
M. Osman, Zahraa Elhassan |
title |
Hardware Implementation of an Optimized Processor Architecture for SOBEL Image Edge Detection Operator |
title_short |
Hardware Implementation of an Optimized Processor Architecture for SOBEL Image Edge Detection Operator |
title_full |
Hardware Implementation of an Optimized Processor Architecture for SOBEL Image Edge Detection Operator |
title_fullStr |
Hardware Implementation of an Optimized Processor Architecture for SOBEL Image Edge Detection Operator |
title_full_unstemmed |
Hardware Implementation of an Optimized Processor Architecture for SOBEL Image Edge Detection Operator |
title_sort |
hardware implementation of an optimized processor architecture for sobel image edge detection operator |
publishDate |
2010 |
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http://eprints.utp.edu.my/4235/1/icias-zahraa.pdf%3Fattachauth%3DANoY7crGR_WIYeVabAL__dLRXvdX42BGyBR4YsQ9Kkx6IwE8CDbXtNR7_0B_ZTgvdQGBS4SOvZFnup4DYCRrKwVdBQDpkxCwTpPqxN0UBWC3qDBZtA0dFY_NPY_dOzLFSa8s1EK1SNOH2pIE_su-IOue63oC2sz7OYRD1gJpUHOQDPUlyNxbDAH186cC76O_g8YrPrRtGEjq%26attredirects%3D0 http://www.utp.edu.my/icias2010/ http://eprints.utp.edu.my/4235/ |
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1738655328250101760 |
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13.160551 |