Optimization of Processor Architecture for Sobel Real-Time Edge Detection Using FPGA
This paper presents an optimized processor architecture for Sobel edge detection operator on field programmable gate arrays (FPGA). The processor is optimized by the use of several optimization techniques that aim to increase the processor throughput and reduce the processor logic utilization. FPGA...
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Main Authors: | , , , |
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Format: | Article |
Published: |
2013
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Online Access: | http://eprints.utp.edu.my/11946/ |
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