Optimization of Processor Architecture for Image Edge Detection Filter
In this paper, a dedicated edge detection processor architecture based on field programmable gate arrays is presented. The architecture is an optimization of the Sobel edge detection filter, specifically focusing on the reduction of the computation time. The proposed architecture reduces the number...
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| Main Authors: | , , |
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| Format: | Conference or Workshop Item |
| Published: |
2010
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| Subjects: | |
| Online Access: | http://eprints.utp.edu.my/2089/1/Cambridg_paper_-_final_version.pdf http://dx.doi.org/10.1109/UKSIM.2010.123 http://eprints.utp.edu.my/2089/ |
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