Automatic Generation of Test Instructions for Structural Faults in Processor Cores using Satisfiability

• Main Authors: Shaheen, Ateeq-Ur-Rehman, Hussin, Fawnizu Azmadi, Hamid, Nor Hisham, Zain Ali, Noohul Basheer
• Format: Conference or Workshop Item
• Published: 2013
• Online Access: http://eprints.utp.edu.my/11973/1/ISOCC2013.pdf; http://eprints.utp.edu.my/11973/

Instruction execution from the cache to detect the faulty chips in native mode has proven its effectiveness with high performance and low power consumption. Gate-level ATPG are time expensive and difficult to implement for large design. In this paper, we proposed an RTL-based methodology framework t...