Thermal-aware directional and adaptive routing algorithm for 3d network-on-chip
Due to the tier architecture of 3D network-on-chip (3D-NoC), reducing the thermal hotspot within the chip is challenging as a cooling mechanism that lies merely on the single side of a chip. High power density in 3D NoC is responsible for reliability degradation and thermal difficulties. Thermal-awa...
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Main Authors: | , |
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Format: | Article |
Language: | English |
Published: |
Institute of Advanced Engineering and Science
2022
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Subjects: | |
Online Access: | http://eprints.utm.my/id/eprint/98697/1/MuhammadKaleem2022_ThermalAwareDirectionalandAdaptive.pdf http://eprints.utm.my/id/eprint/98697/ http://dx.doi.org/10.11591/ijeecs.v27.i2.pp1051-1061 |
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Summary: | Due to the tier architecture of 3D network-on-chip (3D-NoC), reducing the thermal hotspot within the chip is challenging as a cooling mechanism that lies merely on the single side of a chip. High power density in 3D NoC is responsible for reliability degradation and thermal difficulties. Thermal-aware routing becomes substantial to handle thermal difficulties and diffusion of heat to the cooler regions. Thermal-aware routing focuses on bypassing hotspot areas by selecting cooler areas. Existing thermal-aware routing algorithms adopt slightly cooler but longer and extended paths, due to lack of ability to know the proximity of the destination's location, which aggravate thermal issues. This work presents a novel thermal-aware directional and adaptive routing algorithm. Objective of the proposed algorithm is to strive to find the best possible neighbour to reach closer to the proximity of the destination. The proposed algorithm can adaptively choose any suitable neighbour that can lead packets closer to the destination at each intermediate node. The performance of the proposed algorithm is evaluated and compared with existing thermal-aware routing algorithm in a simulator environment. Simulation results demonstrate that the proposed method outperformed its counterpart in terms of average delay with 11-26% improvement, total hop counts with 8-24% reduction under various traffic conditions and improvement in overall thermal profiling of the chip. |
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