A 2 Kbit memory array of mixed-VT GC-eDRAM implemented in 130nm standard CMOS technology
The minimization of very large-scale integrated circuits is facing a great challenge as the demands of devices with low power, and high-performance characteristics have intensely increased. Achieving a downscaled embedded memory design with a low leakage power, high stability, and minimized area bec...
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my.utm.981512022-12-04T09:47:05Z http://eprints.utm.my/id/eprint/98151/ A 2 Kbit memory array of mixed-VT GC-eDRAM implemented in 130nm standard CMOS technology Abdo, Hussien Alias, N. Ezaila Hamzah, Afiq Kamisian, Izam Tan, M. L. Peng Sheikh, U. Ullah TK Electrical engineering. Electronics Nuclear engineering The minimization of very large-scale integrated circuits is facing a great challenge as the demands of devices with low power, and high-performance characteristics have intensely increased. Achieving a downscaled embedded memory design with a low leakage power, high stability, and minimized area became harder to achieve with SRAM based memories. A memory structure which is of great interest is the Gain-Cell eDRAM (GC-eDRAM). It has a high density, low leakage, logic compatibility, and suitable for two-port operations. This work presents a novel cell topology of mixed-VT 3T GC-eDRAM to improve the data retention times (DRT) and speed for better energy efficiency in embedded memories. Simulations work is conducted to evaluate the performance of a 2 Kbit mixed-VT 3T GC-eDRAM array layout until corner process simulation. Mentor Graphics Software is used to design and simulate each of the block diagrams in 130nm CMOS process technology. The array demonstrated successful operation at 400Mhz under a 1V supply and is almost 60-75% less in area than 6T SRAM in the same technology. The retention power showed about 80-90% lower power consumption as compared to the existing 6T and 4T ULP SRAMs (others' work). 2021 Conference or Workshop Item PeerReviewed Abdo, Hussien and Alias, N. Ezaila and Hamzah, Afiq and Kamisian, Izam and Tan, M. L. Peng and Sheikh, U. Ullah (2021) A 2 Kbit memory array of mixed-VT GC-eDRAM implemented in 130nm standard CMOS technology. In: 13th IEEE Regional Symposium on Micro and Nanoelectronics, RSM 2021, 2 - 4 August 2021, Virtual, Kuala Lumpur. http://dx.doi.org/10.1109/RSM52397.2021.9511591 |
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TK Electrical engineering. Electronics Nuclear engineering Abdo, Hussien Alias, N. Ezaila Hamzah, Afiq Kamisian, Izam Tan, M. L. Peng Sheikh, U. Ullah A 2 Kbit memory array of mixed-VT GC-eDRAM implemented in 130nm standard CMOS technology |
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The minimization of very large-scale integrated circuits is facing a great challenge as the demands of devices with low power, and high-performance characteristics have intensely increased. Achieving a downscaled embedded memory design with a low leakage power, high stability, and minimized area became harder to achieve with SRAM based memories. A memory structure which is of great interest is the Gain-Cell eDRAM (GC-eDRAM). It has a high density, low leakage, logic compatibility, and suitable for two-port operations. This work presents a novel cell topology of mixed-VT 3T GC-eDRAM to improve the data retention times (DRT) and speed for better energy efficiency in embedded memories. Simulations work is conducted to evaluate the performance of a 2 Kbit mixed-VT 3T GC-eDRAM array layout until corner process simulation. Mentor Graphics Software is used to design and simulate each of the block diagrams in 130nm CMOS process technology. The array demonstrated successful operation at 400Mhz under a 1V supply and is almost 60-75% less in area than 6T SRAM in the same technology. The retention power showed about 80-90% lower power consumption as compared to the existing 6T and 4T ULP SRAMs (others' work). |
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Conference or Workshop Item |
author |
Abdo, Hussien Alias, N. Ezaila Hamzah, Afiq Kamisian, Izam Tan, M. L. Peng Sheikh, U. Ullah |
author_facet |
Abdo, Hussien Alias, N. Ezaila Hamzah, Afiq Kamisian, Izam Tan, M. L. Peng Sheikh, U. Ullah |
author_sort |
Abdo, Hussien |
title |
A 2 Kbit memory array of mixed-VT GC-eDRAM implemented in 130nm standard CMOS technology |
title_short |
A 2 Kbit memory array of mixed-VT GC-eDRAM implemented in 130nm standard CMOS technology |
title_full |
A 2 Kbit memory array of mixed-VT GC-eDRAM implemented in 130nm standard CMOS technology |
title_fullStr |
A 2 Kbit memory array of mixed-VT GC-eDRAM implemented in 130nm standard CMOS technology |
title_full_unstemmed |
A 2 Kbit memory array of mixed-VT GC-eDRAM implemented in 130nm standard CMOS technology |
title_sort |
2 kbit memory array of mixed-vt gc-edram implemented in 130nm standard cmos technology |
publishDate |
2021 |
url |
http://eprints.utm.my/id/eprint/98151/ http://dx.doi.org/10.1109/RSM52397.2021.9511591 |
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1751536154788757504 |
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13.160551 |