VLSI design of a split parallel two-dimensional HEVC transform
This paper proposes a highly parallel two-dimensional (2D) HEVC transform hardware architecture, implemented in 32-nm VLSI technology. The design allows very high-resolution and frame-rate video coding by way of a very fast HEVC transform operations. It is based on a split architecture, where the in...
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Main Authors: | , , , |
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Format: | Conference or Workshop Item |
Published: |
2021
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Subjects: | |
Online Access: | http://eprints.utm.my/id/eprint/95905/ http://dx.doi.org/10.1007/978-981-16-0749-3_32 |
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