VLSI design of a split parallel two-dimensional HEVC transform
This paper proposes a highly parallel two-dimensional (2D) HEVC transform hardware architecture, implemented in 32-nm VLSI technology. The design allows very high-resolution and frame-rate video coding by way of a very fast HEVC transform operations. It is based on a split architecture, where the in...
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my.utm.959052022-06-29T07:28:43Z http://eprints.utm.my/id/eprint/95905/ VLSI design of a split parallel two-dimensional HEVC transform Awab, Ainy Haziyah Ab. Rahman, Ab. Al-Hadi Kamisian, Izam Rusli, Mohd. Shahrizal TK Electrical engineering. Electronics Nuclear engineering This paper proposes a highly parallel two-dimensional (2D) HEVC transform hardware architecture, implemented in 32-nm VLSI technology. The design allows very high-resolution and frame-rate video coding by way of a very fast HEVC transform operations. It is based on a split architecture, where the individual transform type and size is separated into its own core, therefore enables pixel-level parallelism in the 2D parallel and folded structures. This work also implements the full specification of the HEVC transform for both the DCT and DST transforms, with performance, power, and area analyses for the two structures. Results show very significant speed up over existing unified architectures, with only a relatively modest increase in total gate count. The design is suitable for applications that require very high video resolution and frame rate. 2021-01 Conference or Workshop Item PeerReviewed Awab, Ainy Haziyah and Ab. Rahman, Ab. Al-Hadi and Kamisian, Izam and Rusli, Mohd. Shahrizal (2021) VLSI design of a split parallel two-dimensional HEVC transform. In: 2nd International Conference on Electrical and Electronics Engineering, ICEEE 2021, 2 January 2021 - 3 January 2021, Virtual, Online. http://dx.doi.org/10.1007/978-981-16-0749-3_32 |
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TK Electrical engineering. Electronics Nuclear engineering Awab, Ainy Haziyah Ab. Rahman, Ab. Al-Hadi Kamisian, Izam Rusli, Mohd. Shahrizal VLSI design of a split parallel two-dimensional HEVC transform |
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This paper proposes a highly parallel two-dimensional (2D) HEVC transform hardware architecture, implemented in 32-nm VLSI technology. The design allows very high-resolution and frame-rate video coding by way of a very fast HEVC transform operations. It is based on a split architecture, where the individual transform type and size is separated into its own core, therefore enables pixel-level parallelism in the 2D parallel and folded structures. This work also implements the full specification of the HEVC transform for both the DCT and DST transforms, with performance, power, and area analyses for the two structures. Results show very significant speed up over existing unified architectures, with only a relatively modest increase in total gate count. The design is suitable for applications that require very high video resolution and frame rate. |
format |
Conference or Workshop Item |
author |
Awab, Ainy Haziyah Ab. Rahman, Ab. Al-Hadi Kamisian, Izam Rusli, Mohd. Shahrizal |
author_facet |
Awab, Ainy Haziyah Ab. Rahman, Ab. Al-Hadi Kamisian, Izam Rusli, Mohd. Shahrizal |
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Awab, Ainy Haziyah |
title |
VLSI design of a split parallel two-dimensional HEVC transform |
title_short |
VLSI design of a split parallel two-dimensional HEVC transform |
title_full |
VLSI design of a split parallel two-dimensional HEVC transform |
title_fullStr |
VLSI design of a split parallel two-dimensional HEVC transform |
title_full_unstemmed |
VLSI design of a split parallel two-dimensional HEVC transform |
title_sort |
vlsi design of a split parallel two-dimensional hevc transform |
publishDate |
2021 |
url |
http://eprints.utm.my/id/eprint/95905/ http://dx.doi.org/10.1007/978-981-16-0749-3_32 |
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1738510297637847040 |
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13.160551 |