16-bit fault tolerant sparse Kogge Stone Adder using 0.18µm CMOS technology

• Main Authors: Chang, Chin Kai, Isaak, Suhaila, Yusof, Yusmeeraz
• Format: Conference or Workshop Item
• Published: 2020
• Subjects: TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://eprints.utm.my/id/eprint/92863/; http://dx.doi.org/10.1109/ICSE49846.2020.9166865

Fault-tolerant architecture plays a crucial role in the safety and mission-critical application such as space and medical application. These applications require high reliability to maintain continuous operation without fault. The tremendous increase in the integration density and the downscaling of the nanotechnology cause the system exposed to the soft error more frequently. This project concerns the development of a 16-bit fault tolerant sparse Kogge Stone Adder (KSA) by implementing Triple Modular Redundancy (TMR) approach. The results show that the fault tolerability had been greatly improved at almost double the masking rate of the adder alone and can be operated at the maximum frequency of 166.67 MHz. Application-Specific Integrated Circuit (ASIC) implementation using Silterra 0.18 μm CMOS technology is conducted using Synopsys Electronic Design Automation tools.