The design and implementation of a low-power gating scan element in 32/28 nm CMOS technology
Excessive power consumption during test application time has severely negative effects on chip reliability since it has an inevitable role in hot spots that appear, degradation of performance, circuit premature destruction, and functional failures. In scan-based designs, rippling transitions caused...
Saved in:
| Main Authors: | , , |
|---|---|
| Format: | Article |
| Published: |
MDPI AG
2017
|
| Subjects: | |
| Online Access: | http://eprints.utm.my/id/eprint/80792/ http://dx.doi.org/10.3390/jlpea7020007 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|