ProNoC: a low latency network-on-chip based many-core system-on-chip prototyping platform

• Main Authors: Monemi, A., Tang, J. W., Palesi, M., Marsono, M. N.
• Format: Article
• Published: Elsevier B.V. 2017
• Subjects: TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://eprints.utm.my/id/eprint/76963/; https://www.scopus.com/inward/record.uri?eid=2-s2.0-85028742066&doi=10.1016%2fj.micpro.2017.08.007&partnerID=40&md5=de9353a3876537551d45038414dae500

Network-on-chip (NoC) is an emerging interconnect infrastructure to address the scalability limitation of conventional shared bus architecture for many-core system-on-chip (MCSoC). Current field-programmable gate arrays (FPGAs) have over million lookup tables, making it possible to prototype a compl...