Characterization of strained silicon MOSFET using semiconductor TCAD tools

• Main Authors: Wong, Yah Jin, Saad, Ismail, Ismail, Razali
• Format: Conference or Workshop Item
• Language: English
• Published: 2006
• Subjects: TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://eprints.utm.my/id/eprint/7495/1/Razali_Ismail_2006_Characterization_of_Strained_Silicon_MOSFET.pdf; http://eprints.utm.my/id/eprint/7495/; http://dx.doi.org/10.1109/SMELEC.2006.380774

The paper is looking into the enhancement of conventional PMOS by incorporating a strained silicon within the channel and bulk of semiconductor. A detailed 2D process simulation of strained silicon PMOS (SSPMos) and its electrical characterization was done using TCAD tool. With the oxide thickness, Tox of 16 nm and germanium concentration of 35%, the threshold voltage Vt for the strained Si and conventional PMOS is -0.5067V and -0.9290V respectively. This indicates that the strained silicon had lower power consumption. Beside that, the drain induced barrier lowering (DIBL) value for the strained PMOS is 0.3034V and the conventional PMOS is 0.4747V, which shows a better performance for strained silicon as compared to conventional PMOS. In addition, the output characteristics were also obtained for SSPMos which showed an improvement of drain current compared with conventional PMOS.