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Low cost pipelined FPGA architecture of Harris Corner Detector for real-time applications

In this paper, we present a low cost, pipelined FPGA architecture of a Harris Corner Detector. The platform is Altera Cyclone IV on a DE2-115 development board. The pipeline is composed of multiple stages, between which data flows without temporary full-frame buffering. The architecture was tested u...

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Main Authors: Orabi, H., Shaikh-Husin, N., Sheikh, U. U.
Format: Conference or Workshop Item
Published: Institute of Electrical and Electronics Engineers Inc. 2016
Subjects:
TK Electrical engineering. Electronics Nuclear engineering
Online Access:http://eprints.utm.my/id/eprint/73462/
https://www.scopus.com/inward/record.uri?eid=2-s2.0-84964801925&doi=10.1109%2fICDIM.2015.7381868&partnerID=40&md5=c237a35e9b65102fbbe8cae6309865a5
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spelling my.utm.734622017-11-23T04:17:45Z http://eprints.utm.my/id/eprint/73462/ Low cost pipelined FPGA architecture of Harris Corner Detector for real-time applications Orabi, H. Shaikh-Husin, N. Sheikh, U. U. TK Electrical engineering. Electronics Nuclear engineering In this paper, we present a low cost, pipelined FPGA architecture of a Harris Corner Detector. The platform is Altera Cyclone IV on a DE2-115 development board. The pipeline is composed of multiple stages, between which data flows without temporary full-frame buffering. The architecture was tested using a System Verilog test-bench, enveloped by a MATLAB test-bench, to benefit from the latter's image processing capabilities. The accuracy of the results obtained was tested visually and compared with the results of the same algorithm implemented in MATLAB. The results show a balance between resources utilization and timing performance, compared with recent works. Institute of Electrical and Electronics Engineers Inc. 2016 Conference or Workshop Item PeerReviewed Orabi, H. and Shaikh-Husin, N. and Sheikh, U. U. (2016) Low cost pipelined FPGA architecture of Harris Corner Detector for real-time applications. In: 10th International Conference on Digital Information Management, ICDIM 2015, 21-23 Oct 2015, South Korea. https://www.scopus.com/inward/record.uri?eid=2-s2.0-84964801925&doi=10.1109%2fICDIM.2015.7381868&partnerID=40&md5=c237a35e9b65102fbbe8cae6309865a5
institution Universiti Teknologi Malaysia
building UTM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Teknologi Malaysia
content_source UTM Institutional Repository
url_provider http://eprints.utm.my/
topic TK Electrical engineering. Electronics Nuclear engineering
spellingShingle TK Electrical engineering. Electronics Nuclear engineering
Orabi, H.
Shaikh-Husin, N.
Sheikh, U. U.
Low cost pipelined FPGA architecture of Harris Corner Detector for real-time applications
description In this paper, we present a low cost, pipelined FPGA architecture of a Harris Corner Detector. The platform is Altera Cyclone IV on a DE2-115 development board. The pipeline is composed of multiple stages, between which data flows without temporary full-frame buffering. The architecture was tested using a System Verilog test-bench, enveloped by a MATLAB test-bench, to benefit from the latter's image processing capabilities. The accuracy of the results obtained was tested visually and compared with the results of the same algorithm implemented in MATLAB. The results show a balance between resources utilization and timing performance, compared with recent works.
format Conference or Workshop Item
author Orabi, H.
Shaikh-Husin, N.
Sheikh, U. U.
author_facet Orabi, H.
Shaikh-Husin, N.
Sheikh, U. U.
author_sort Orabi, H.
title Low cost pipelined FPGA architecture of Harris Corner Detector for real-time applications
title_short Low cost pipelined FPGA architecture of Harris Corner Detector for real-time applications
title_full Low cost pipelined FPGA architecture of Harris Corner Detector for real-time applications
title_fullStr Low cost pipelined FPGA architecture of Harris Corner Detector for real-time applications
title_full_unstemmed Low cost pipelined FPGA architecture of Harris Corner Detector for real-time applications
title_sort low cost pipelined fpga architecture of harris corner detector for real-time applications
publisher Institute of Electrical and Electronics Engineers Inc.
publishDate 2016
url http://eprints.utm.my/id/eprint/73462/
https://www.scopus.com/inward/record.uri?eid=2-s2.0-84964801925&doi=10.1109%2fICDIM.2015.7381868&partnerID=40&md5=c237a35e9b65102fbbe8cae6309865a5
_version_ 1643656667166932992
score 13.188404

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