FPGA implementation of RANSAC algorithm for real-time image geometry estimation
Random Sample Consensus (RANSAC) is commonly used in many estimation tasks especially in computer vision applications due to its simplicity. This paper presents a hardware/software co-design implementation of RANSAC algorithm for real-time affine geometry estimation on a field programmable gate arra...
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my.utm.592762021-09-05T04:42:38Z http://eprints.utm.my/id/eprint/59276/ FPGA implementation of RANSAC algorithm for real-time image geometry estimation Tang, Jia Wei Shaikh Husin, Nasir Sheikh, Usman Ullah TK Electrical engineering. Electronics Nuclear engineering Random Sample Consensus (RANSAC) is commonly used in many estimation tasks especially in computer vision applications due to its simplicity. This paper presents a hardware/software co-design implementation of RANSAC algorithm for real-time affine geometry estimation on a field programmable gate array (FPGA) platform. Double buffering technique is used to store and process data in pipeline. Experimental result shows that the proposed system managed to speed up the software process by about 11.4 times for 100 data points. The proposed architecture was also tested on Altera DE2-115 with 100 MHz NiosII Processor running to handle a video stream of 30 frames per second. 2014-01-06 Conference or Workshop Item PeerReviewed application/pdf en http://eprints.utm.my/id/eprint/59276/1/TangJiaWei2013_FPGAImplementationofRANSACAlgorithm.pdf Tang, Jia Wei and Shaikh Husin, Nasir and Sheikh, Usman Ullah (2014) FPGA implementation of RANSAC algorithm for real-time image geometry estimation. In: 2013 11th IEEE Student Conference on Research and Development, SCOReD 2013, 16 December 2013 - 17 December 2013, Putrajaya, Malaysia. http://dx.doi.org/10.1109/SCOReD.2013.7002592 |
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TK Electrical engineering. Electronics Nuclear engineering Tang, Jia Wei Shaikh Husin, Nasir Sheikh, Usman Ullah FPGA implementation of RANSAC algorithm for real-time image geometry estimation |
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Random Sample Consensus (RANSAC) is commonly used in many estimation tasks especially in computer vision applications due to its simplicity. This paper presents a hardware/software co-design implementation of RANSAC algorithm for real-time affine geometry estimation on a field programmable gate array (FPGA) platform. Double buffering technique is used to store and process data in pipeline. Experimental result shows that the proposed system managed to speed up the software process by about 11.4 times for 100 data points. The proposed architecture was also tested on Altera DE2-115 with 100 MHz NiosII Processor running to handle a video stream of 30 frames per second. |
format |
Conference or Workshop Item |
author |
Tang, Jia Wei Shaikh Husin, Nasir Sheikh, Usman Ullah |
author_facet |
Tang, Jia Wei Shaikh Husin, Nasir Sheikh, Usman Ullah |
author_sort |
Tang, Jia Wei |
title |
FPGA implementation of RANSAC algorithm for real-time image geometry estimation |
title_short |
FPGA implementation of RANSAC algorithm for real-time image geometry estimation |
title_full |
FPGA implementation of RANSAC algorithm for real-time image geometry estimation |
title_fullStr |
FPGA implementation of RANSAC algorithm for real-time image geometry estimation |
title_full_unstemmed |
FPGA implementation of RANSAC algorithm for real-time image geometry estimation |
title_sort |
fpga implementation of ransac algorithm for real-time image geometry estimation |
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2014 |
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http://eprints.utm.my/id/eprint/59276/1/TangJiaWei2013_FPGAImplementationofRANSACAlgorithm.pdf http://eprints.utm.my/id/eprint/59276/ http://dx.doi.org/10.1109/SCOReD.2013.7002592 |
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13.189025 |