Silicon nanowire field-effect transistor (SiNWFET) and its circuit level performance

• Main Author: Bahador, Siti Norazlin
• Format: Thesis
• Language: English
• Published: 2014
• Subjects: TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://eprints.utm.my/id/eprint/48023/25/SitiNorazlinBahadorMFKE2014.pdf; http://eprints.utm.my/id/eprint/48023/

Since the number of transistors on Integrated Circuit (IC) double every 18 months, the scaling of a device in nanometer is highly required. Due to the downscaling process, conventional Metal-Oxide-Semiconductor Field-Effect- Transistors (MOSFET) lead to the short-channel effects, gate-leakage current and interconnect problem. Hence, the introduction of new structure of Silicon Nanowire (SiNW) is necessary and crucial. The SiNW had been proven with an ability to effectively suppress the off-leakage current with its Gate-All-Around (GAA) configuration when compared to the planar MOSFET. In addition, the SiNWFET will be considered to be a promising structure for ultra-CMOS devices to the extend device approaching their downsized limits. This research is accomplished by developing a model of Silicon Nanowire (SiNW) with GAA configuration in MATLAB. In order to evaluate the performance in digital level, HSPICE is used to create its own library based on developed model. The on-current as high as 5µA can be achieved by the n-type SiNWFET while p-type SiNWFET can reach until same 5µA saturation current. Both models show symmetrical results indicating a fast switching inverter. These models are utilized to build some logic gates in order to further examining their performance in circuit application. The SiNWFET performance is also compared with the nano-MOSFET for benchmarking. The finding of this research is that the SiNWFET model is proven to have better performance than nano-MOSFET in terms of Power Delay Product and Energy Delay Product. Furthermore, when Tox is reduced and Rsi, Nd and L are increased, a significant device improvement of SiNWFET GAA is attained. This is achieved by having reduced Drain Induced Barrier Lowering, Subthreshold Slope and providing higher Ion/Ioff current ratio by improving the parameter in the device modelling of SiNWFET.